ESD evaluation of a low voltage triggering SCR (LVTSCR) device submitted to transmission line pulse (TLP) test

Author:

Guilhaume A,Galy P,Chante J.P,Foucher B,Bardy S,Blanc F

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Biotechnology,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. K. Esmark, W. Stadler, et al., Advanced 2D/3D ESD device simulation—a powerful tool already used in a pre-Si phase, Proceedings of the EOS/ESD Symposium, 2000, pp. 420–429.

2. M. Mergens, On-chip ESD protection in integrated circuits: device physics, modelling, circuit simulation, Ph.D. Thesis, Series in Microelectronics, Vol. 116, 2001.

3. A. Stricker, W. Fichtner, et al., Characterization and optimization of a bipolar ESD-device by measurements and simulations, Proceedings of the Symposium EOS/ESD, 1998, pp. 290–300.

4. ESD in Silicon Integrated Circuits;Amerasakera,1995

5. ISE Integrated System Engineering, User's manual release 6.0, Zurich, 1999.

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