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A novel clock generation algorithm for system-on-chip based on least common multiple

  • Published:2014-10 Issue:7 Volume:40 Page:2113-2125
  • ISSN:0045-7906
  • Container-title:Computers & Electrical Engineering
  • language:en
  • Short-container-title:Computers & Electrical Engineering

Author:

Reuben John,Kittur Harish M.,Shoaib Mohd

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference25 articles.

1. System-on-a-chip: design and test;Rajsuman,2000

2. IP strategies for SoC design;Jeong;Synopsys J,2011

3. Interconnect-centric design for advanced SoC and NoC,2004

4. System-on-chip: reuse and integration;Saleh;Proc IEEE,2006

5. IP datasheets; 2013. .

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2. References;CAD of Circuits and Integrated Systems;2020-06-30

3. Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-02

4. A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM;2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC);2019-10

5. An Efficient Clock Generation Algorithm for System-on-Chip Based on Least Common Multiple;Journal of Circuits, Systems and Computers;2019-07
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