A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM-Reference-Cited by-同舟云学术

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A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Published:2019-10 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
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Author:

Reuben John,Fey Dietmar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8894146/8906892/08906921.pdf?arnumber=8906921

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. A novel time-domain in-memory computing unit using STT-MRAM;Microelectronic Engineering;2024-01

3. ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

4. Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

5. A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories;2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST);2023-06-28

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