Mitigation of soft errors in SRAM-based FPGAs using CAD tools

Author:

Bahramnejad Somayeh,Zarandi Hamid R.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference32 articles.

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3. Asadi H, Tahoori MB. Soft error rate estimation and mitigation for SRAM-based FPGAs. In: ACM/SIGDA international symposium on field-programmable gate arrays; February 2005. p. 149–60.

4. Bolchini C, Miele A, Santambrogio MD. TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs. In: IEEE international symposium on defect and fault-tolerance in VLSI systems; September 2007. p. 87–95.

5. Ross D, Vellacott O, Turner M. An FPGA-based hardware accelerator for image processing. In: Proceedings of the international workshop on field-programmable logic and applications; 1993. p. 299–306.

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