Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect transistors

Author:

Butola RajatORCID,Li YimingORCID,Kola Sekhar Reddy,Akbar Chandni,Chuang Min-Hui

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference30 articles.

1. 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued moore's law scaling;Huang,2020

2. Numerical investigation and temperature-based analysis of the analog performance of fully gate-covered junctionless FinFET;Mangal;Comput Electr Eng,2022

3. Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers;Kola,2020

4. DC Characteristics and Dynamic Properties of Multi-Channel Nanosheet MOSFETs with and without Tungsten Metal Sidewall for Sub-3-nm Technological Nodes;Chuang;ECS Journal of Solid State Science and Technology,2022

5. Characteristics of stacked gate-all-around Si nanosheet MOSFETs with metal sidewall source/drain and their impacts on CMOS circuit properties;Sung;IEEE Trans Electron Devices,2021

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