Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Author:

Mewada Manan,Zaveri Mazad,Gandhi Ratnik,Thakker Rajesh

Publisher

Elsevier BV

Subject

General Engineering

Reference21 articles.

1. CMOS VLSI design: a circuits and systems perspective;Weste,2015

2. Zhang, Mingyan, Jiangmin Gu, and Chip-Hong Chang. "A novel hybrid pass logic with static CMOS output drive full-adder cell." In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS’03., vol. 5, pp. V-V. IEEE, 2003.

3. A framework for fair performance evaluation of 1-bit full adder cells.;Shams,1999

4. Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style;Goel;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006

5. Performance analysis of low-power 1-bit CMOS full adder cells.;Shams;IEEE transactions on very large scale integration (VLSI) systems,2002

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1. Design of Multi-Bit Full Adder Using Low Power m-GDI Technique;2023 IEEE World Conference on Applied Intelligence and Computing (AIC);2023-07-29

2. A Modified Full Adder (MFA) with an introverted unique Design for Low Power VLSI Circuit Applications;2022 International Conference on Smart Technologies and Systems for Next Generation Computing (ICSTSN);2022-03-25

3. Spin Wave Based Full Adder;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

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