Design of Low Power, Low Jitter PLL for WiMAX Application in 0.18µm CMOS Process-Reference-Cited by-同舟云学术

Design of Low Power, Low Jitter PLL for WiMAX Application in 0.18µm CMOS Process

Published:2019 Issue: Volume:152 Page:390-397
ISSN:1877-0509
Container-title:Procedia Computer Science
language:en
Short-container-title:Procedia Computer Science

Author:

Kailuke Aniruddha,Agrawal Pankaj,Kshirsagar R.V.

Publisher

Elsevier BV

Subject

General Engineering

Reference19 articles.

1. Design of Analog CMOS Integrated Circuits;Razavi,2010

2. Fast Frequency Acquisition Phase-Frequency Detectors for GSamples/s Phase-Locked Loops;Mansuri;IEEE Journal of Solid-State Circuits,2002

3. Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition. IEEE Trans CircSyst II:;Wu-Hsin;Express Briefs,2010

4. Z. A. Sabbagh.(2007) “0.18µm Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld’s Phase-Locked-Loop Systems.” Thesis.

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