Turn-on speed of grounded gate nMOS ESD protection transistors-Reference-Cited by-同舟云学术

Turn-on speed of grounded gate nMOS ESD protection transistors

Published:1996-11 Issue:11-12 Volume:36 Page:1735-1738
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Meneghesso G.,Luchies J.R.M.,Kuper F.G.,Mouthaan A.J.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Draft standard for Electrostatic Discharge (ESD) Sensitivity testing, Charged Device Model (CDM) Component testing, EOS/ESD-S5.1–1993, EOS/ESD Ass. Inc., USA.

2. Advanced CMOS Protection Device Trigger Mechanisms During CDM;Duvvurry,1995

3. Fast Turn-On Of An NMOS ESD Protection Transistor; Measurements and Simulation;Luchies,1994

4. Zeitaufgelöste Untersuchungen des Snapbackverhaltens eines ESD-Schutztransistors;Kropf,1993

5. NMOS transistors behaviour under CDM stress conditions and correlation to other ESD models;Verhaeghe,1995

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process;IEICE Transactions on Electronics;2016

2. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology;Solid-State Electronics;2016-01

3. Drain breakdown in submicron MOSFETs: a review;Microelectronics Reliability;2000-01

4. A simulation analysis of quarter-micron CMOS LSI input circuit behavior under CDM-ESD for protection device improvement;Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396)