1. Accelerated SAT-based scheduling of control/data flow graphs;Memik,2002
2. Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based boolean SAT;Nam,1999
3. Symbolic model checking using SAT procedures instead of BDDs;Biere,1999
4. Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic;Bryant;ACM Trans. Comput. Log.,2001
5. The complexity of theorem-proving procedures;Cook,1971