Reliability issues of silicon LSIs facing 100-nm technology node-Reference-Cited by-同舟云学术

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Reliability issues of silicon LSIs facing 100-nm technology node

Published:2002-04 Issue:4-5 Volume:42 Page:493-506
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Takeda Eiji,Murakami Eiichi,Torii Kazuyoshi,Okuyama Yutaka,Ebe Eishi,Hinode Kenji,Kimura Shin'ichiro

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference68 articles.

1. International Technology Roadmap of Semiconductor, 2000

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1. The tunnelling and electron injection reliabilities for FG transistors;Microelectronics International;2014-04-29

2. Simulation of BTI-Related Time-Dependent Variability in CMOS Circuits;Bias Temperature Instability for Devices and Circuits;2013-09-10

3. Deep hole trapping effects in the degradation mechanisms of 6.5–2 nm thick gate-oxide PMOSFETs;Microelectronic Engineering;2004-04

4. Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides;Microelectronics Reliability;2004-01

5. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing;Journal of Applied Physics;2003-07

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