Author:
Su Jiong-Guang,Wong Shyh-Chyi,Huang Chi-Tsung
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference21 articles.
1. Rodder M, Hong QZ, Nandakumar M, Aur S, Hu JC, Chen I-C. A sub-0.18 μm gate length CMOS technology of high performance (1.5 V) and low power (1.0 V) In: Technical Digest of IEEE International Electron Devices Meeting, 1996. p. 563–66
2. Hwang H, Lee D-H, Hwang JM. Degradation of MOSFETs drive current due to Halo ion implantation. In: Technical Digest of IEEE International Electron Devices Meeting, 1996. p. 567–70
3. Supply and threshold voltage scaling for low power CMOS;Gonzalez;IEEE J Solid-State Circuits,1996
4. A charge sheet capacitance model of short channel MOSFETs for SPICE;Park;IEEE Trans Electron Devices,1991
5. Hori T. A 0.1 μm CMOS technology with tilt implanted punchthrough stopper (TIPS) In: Technical Digest of IEEE International Electron Devices Meeting, 1994. p. 75–8
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