A breakdown voltage model for implanted resurf p-LDMOS device on n+ buried layer
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference6 articles.
1. BICMOS Technology and Applications;Alvarez,1989
2. Breakdown walkout and its reduction in high-voltage pLDMOS transistors on thin epitaxial layer
3. Calculation of avalanche breakdown voltages of silicon p-n junctions
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Two‐dimensional simulation studies of the breakdown voltage of a p channel LDMOS;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2021-02-14
2. Anomalous output characteristics shrinkage in STI-LDMOS transistor after repetitive I-V scanning measurements;Superlattices and Microstructures;2019-04
3. Analytical modelling for the RESURF effect in JI and SOI power devices;IEE Proceedings - Circuits, Devices and Systems;2002-12-01
4. Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO2 implant mask;IEEE Electron Device Letters;1995-09
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