Analytical modelling for the RESURF effect in JI and SOI power devices
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20020517?crawler=true&mimetype=application/pdf
Reference17 articles.
1. Medici, User's manual version 1999.2.0, Avant!, 1999
2. Optimization of RESURF LDMOS transistors: an analytical approach
3. An analytical model of the breakdown voltage and minimum epi layer length for RESURF pn diodes
4. A new analytical model for determination of breakdown voltage of Resurf structures
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1. Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer;Micromachines;2023-04-20
2. Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage;IEEE Access;2020
3. Ideal RESURF Geometries;IEEE Transactions on Electron Devices;2015-10
4. Analysis of simulation approaches for the breakdown characteristics of SOI high-voltage PMOS in a fixed power supply;Superlattices and Microstructures;2015-02
5. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain;Chinese Physics B;2013-02
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