Flexible router architecture for network-on-chip-Reference-Cited by-同舟云学术

Flexible router architecture for network-on-chip

Published:2012-09 Issue:5 Volume:64 Page:1301-1310
ISSN:0898-1221
Container-title:Computers & Mathematics with Applications
language:en
Short-container-title:Computers & Mathematics with Applications

Author:

Sayed Mostafa S.,Shalaby Ahmed,El-Sayed Mohamed,Goulart Victor

Publisher

Elsevier BV

Subject

Computational Mathematics,Computational Theory and Mathematics,Modeling and Simulation

Reference14 articles.

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2. H. Jingcao, R. Marculescu, Application-specific buffer space allocation for networks-on-chip router design, in: Proceeding of the IEEE/ACM International Conference on Computer Aided Design. ICCAD, 2004, pp. 354–361.

3. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, S. Borkar, A 5-GHz mesh interconnect for a teraflops processor, in: Proceeding of the IEEE MICRO, vol. 27, September–October 2007, pp. 51–61.

4. H. Wang, X. Zhu, L. Peh, S. Malik, Orion: a power-performance simulator for interconnection networks, in: Proceeding of the 35th IEEE/ACM Annual International Symposium on Microarchitecture, MICRO-35, November 2002, pp. 294–305.

5. N. Banerjee, P. Vellanki, K. Chatha, A power and performance model for network-on-chip architectures, in: Proceeding of the Design, Automation and Test in Europe Conference and Exhibition, DATE, vol. 2, February 2004, pp. 1250–1255.

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