Mapping matrix multiplication algorithm onto fault-tolerant systolic array-Reference-Cited by-同舟云学术

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Mapping matrix multiplication algorithm onto fault-tolerant systolic array

Published:2004-07 Issue:1-2 Volume:48 Page:275-289
ISSN:0898-1221
Container-title:Computers & Mathematics with Applications
language:en
Short-container-title:Computers & Mathematics with Applications

Author:

Stojanović N.M.,Milovanović E.I.,Stojmenović I.,Milovanović T..,Tokić T.I.

Publisher

Elsevier BV

Subject

Computational Mathematics,Computational Theory and Mathematics,Modeling and Simulation

Reference15 articles.

1. Algorithm-based fault tolerance for matrix operations;Huang;IEEE Trans. Comput.,1984

2. Algorithm based fault-tolerant technique for matrix inversion;Stojčev,1991

3. Fault-tolerant design methodology for systolic array architectures;Esonu,1994

4. Optimal fault-tolerant design approach for VLSI array processors;Zhang,1994

5. Optimal fault-tolerant design approach for VLSI array processors;Zhang,1997

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication;Electronics;2024-05-05

2. Hexagonal arrays for fault-tolerant matrix multiplication;Filomat;2015

3. A class of fault-tolerant systolic arrays for matrix multiplication;Mathematical and Computer Modelling;2011-07

4. Orthogonal fault-tolerant systolic arrays for matrix multiplication;Microelectronics Reliability;2011-03

5. Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules;Journal of Parallel and Distributed Computing;2006-03

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