Parallel realization of the ATM cell header CRC-Reference-Cited by-同舟云学术

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Parallel realization of the ATM cell header CRC

Published:1996-03 Issue:3 Volume:19 Page:257-263
ISSN:0140-3664
Container-title:Computer Communications
language:en
Short-container-title:Computer Communications

Author:

Ng Seong Leong,Dewar Bill

Publisher

Elsevier BV

Subject

Computer Networks and Communications

Reference9 articles.

1. ITU-T Recommendation I.432;B-ISDN User-Network Interface-Physical Layer Specification (03/93),1993

2. Cyclic codes for error detection;Peterson,1961

3. A multi-channel CRC register;Patel;AFIPS Conference Proceedings,1971

4. High-speed parallel CRC circuits in VLSI;Pei;IEEE Trans. on Comm.,1992

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Speed Parallel Architectures for Linear Feedback Shift Registers;IEEE Transactions on Signal Processing;2011-09

2. The Implementation of Scalable ATM Frame Delineation Circuits;Telecommunications and Networking - ICT 2004;2004

3. Designing fault-secure parallel encoders for systematic linear error correcting codes;IEEE Transactions on Reliability;2003-12

4. Automatic generation of parallel CRC circuits;IEEE Design & Test of Computers;2001-05

5. On the cyclic redundancy-check codes with 8-bit redundancy;Computer Communications;1998-08

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