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On the performance of in situ B-doped P+ poly-Si1−xGex gate material for nanometer scale MOS technology

  • Published:2000-08 Issue:8 Volume:44 Page:1425-1429
  • ISSN:0038-1101
  • Container-title:Solid-State Electronics
  • language:en
  • Short-container-title:Solid-State Electronics

Author:

Yousif M.Y.A,Friesel M,Willander M,Lundgren P,Caymax M

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. Design tradeoffs between surface and buried-channel FET's;Hu;IEEE Trans Electron Dev,1985

2. King TJ, Pfiester JR, Shott JD, McVittie JP, Saraswat KC. A polycrystalline-Si1-xGex-gate CMOS technology. IEDM Tech Dig 1990:253–6

3. Kistler N, Woo J. Symmetric CMOS in fully-depleted silicon-on-insulator using P+ -polycrystalline SiGe gate electrodes. IEDM Tech Dig 1993;727–30

4. Observation of reduced boron penetration and gate depletion for poly-Si0.8Ge0.2 gated PMOS devices;Lee;IEEE Electron Dev Lett,1999

5. Enhancement of PMOS device performance with poly-SiGe gate;Lee;IEEE Electron Dev Lett,1999

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