ESD protection in a 3.3 V sub-micron silicided CMOS technology-Reference-Cited by-同舟云学术

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ESD protection in a 3.3 V sub-micron silicided CMOS technology

Published:1993-12 Issue:2-3 Volume:31 Page:111-129
ISSN:0304-3886
Container-title:Journal of Electrostatics
language:en
Short-container-title:Journal of Electrostatics

Author:

Krakauer David

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Biotechnology,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. Output ESD Protection Techniques for Advanced CMOS Processes;Duvvury,1988

2. Thick Oxide ESD performance Under Process Variations;McPhee,1987

3. ESD Protection Reliability in 1μm CMOS Technology;Duvvury,1986

4. A Lumped Element Model for Simulation of ESD Failures in Silicided Devuices;Scott,1986

5. Electrical Overstress in NMOS Silicided Devices;Wilson,1987

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1. A simulation on neutralization performance of a corona discharge air ionizer by using an equivalent circuit;IEEJ Transactions on Electrical and Electronic Engineering;2019-09-30

2. Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process;Solid-State Electronics;2017-09

3. ESD Devices for Input/Output Protection;ESD Protection Device and Circuit Design for Advanced CMOS Technologies;2008

4. Automated X-Ray Elemental Analysis in Three Dimensions Using a Dual Beam-Focused Ion Beam System;Practical Metallography;2007-05-01

5. ESD protection of single output buffers in advanced CMOS technologies;Journal of Electrostatics;2006-02

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