Author:
Rai Shashank,Tiwari Shreyas,Chaudhary Rashi,Saha Rajesh,Sharma Ritu
Reference25 articles.
1. A simulation approach to optimize the electrical parameters of a vertical tunnel FET;Bhuwalka;IEEE Trans. Electron Devices,2005
2. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET;Hisamoto,1989
3. T. Hida, M. Fukaishi, Ohno, A 0.25 mu m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs, in: 1992 International Technical Digest on Electron Devices Meeting, San Francisco, CA, USA, 1992, pp. 982–984, doi: 10.1109/IEDM.1992.307591.
4. 7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn;Gupta;IEEE Trans. Electron Devices,2014
5. Density scaling beyond the FinFET: architecture considerations for gate-all-around CMOS;Guillorn,2016
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献