1. International Technology Roadmap for Semiconductors, 2005 updated version.
2. Post-exposure bake as a process-control parameter for chemically-amplified photoresists;Sturtevant;SPIE Integr. Circuit Metrol., Inspect Process Control,1993
3. Temperature metrology for CD control in DUV lithogragphy;Parker;Semiconduct. Int.,1997
4. Improvements in photolithography performance by controlled baking;Crisalle;SPIE Integr. Circuit Metrol., Inspect Process Control,1988
5. Characterizing photolithographic linewidth sensitivity to process temperature variations for advanced resists using a thermal array;Schaper;Appl. Phys. A: Mater. Sci. Process.,2003