Author:
Arm J.,Bradac Z.,Stohl R.
Subject
Control and Systems Engineering
Reference18 articles.
1. Abate, F., Sterpone, L., Lisboa, C.A., and Carro, L. (2009). New techniques for improving the performance of the lockstep architecture for sees mitigation in fpga embedded processors. IEEE Transactions on Nuclear Science, 1992 – 2000. doi:10.1109/TNS.2009.2013237.
2. Baleani, M., Ferrari, A., Mangeruca, L., Sangiovanni-Vincentelli, A., Peri, M., and Pezzini, S. (2003). Fault-tolerant platforms for automotive safety-critical applications. In In Proc. of the Intl. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, 170– 177. ACM Press.
3. Gomez-Cornejo, J., Zuloaga, A., Kretzschmar, U., and Bidarte, U. (2013). Fast context reloading lockstep approach for seus mitigation in a fpga soft core processor. Industrial Electronics Society, IECON 2013 -39th Annual Conference of the IEEE, 2261 – 2266. doi: 10.1109/IECON.2013.6699483.
4. Hong, C., Benkrid, K., Iturbe, X., and Ebrahim, A. (2012). Design and implementation of fault-tolerant soft processors on fpgas. 22nd International Conference on Field Programmable Logic and Applications (FPL), 683 – 686. doi:10.1109/FPL.2012.6339177.
5. Horst, R., Garcia, D., Bunton, W., Bruckert, W., Fowler, D., Jones, C., Sonnier, D., Watson, W., and Williams, F. (2001). Self-checked, lock step processor pairs. URL http://www.google.com/patents/US6233702. US Patent 6,233,702.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献