1. H. Touati, H. Savoj, B. Lin, R.K. Brayton, A. Sangiovanni-Vincentelli, Implicit enumeration of finite state machines using BDDs, in: Proceedings of the IEEE ICCAD'90, San Jose, CA, USA, November 1990, pp. 130–133
2. Symbolic model checking for sequential circuit verification;Burch;IEEE Transactions on CAD,1994
3. O. Coudert, C. Berthet, J.C. Madre, Verification of sequential machines based on symbolic execution, in: Lecture Notes in Computer Science, vol. 407, Springer, Berlin, 1989, pp. 365–373
4. H. Cho, G.D. Hatchel, E. Macii, B. Plessier, F. Somenzi, Algorithms for approximate FSM traversal, in: Proceedings of the ACM/IEEE DAC'93, Dallas, TX, USA, June 1993, pp. 25–30
5. H. Cho, G.D. Hatchel, E. Macii, M. Poncino, K. Ravi, F. Somenzi, Approximate finite state machine traversal: extensions and new results, in: IWLS'95 – IEEE International Workshop on Logic Synthesis, Lake Tahoe, CA, USA, May 1995