On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation-Reference-Cited by-同舟云学术

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Published:2002-12 Issue:4-5 Volume:48 Page:125-135
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Bakalis Dimitris,Kalligeros Emmanouil,Nikolos Dimitris,Vergos Haridimos T.,Alexiou George

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference22 articles.

1. Digital Systems Testing and Testable Design;Abramovici,1990

2. On low power BIST for carry save array multipliers;Bakalis,1999

3. Low power dissipation in BIST schemes for modified Booth multipliers;Bakalis,1999

4. D. Bakalis, E. Kalligeros, D. Nikolos, H.T. Vergos, G. Alexiou, Low power BIST for Wallace tree-based fast multipliers, Computer Technology Institute Technical Report (TR99/09/07), Patras, Greece, 1999

5. Techniques for minimizing power dissipation in scan and combinational circuits during test application;Dabholkar;IEEE Transactions on CAD of Integrated Circuits and Systems,1998

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