1. Design and implementation of fast booth-2 multiplier on artix FPGA;Behl;ICITETM2020, Proc. Comput. Sci.,2020
2. R.G. Deshmukh, Florida Institute of Technology, Melbourne, FL; Nurettin Besli, “A Novel Redundant Binary Signed Digit (RBSD) Booth’s Encoding” Florida Institute of Technology; Melbourne, FL.
3. A.S. Awwal, J.U. Ahmed, Multiplier Design using RBSD Number System, Wright State University, Computer Science & Engineering Department, Dayton, Ohio.
4. High speed VLSI multiplication algorithm with a redundant binary addition tree;Yasuura;IEEE Trans. Comp.,1985
5. On-line error detectable high-speed multiplier using redundant binary representation and three-rail logic;Takagi;IEEE Trans. Comp,1987