Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap-Reference-Cited by-同舟云学术

Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap

Published:2020-09 Issue: Volume:77 Page:103164
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Satyanarayana B.V.V.,Durga Prakash M.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference18 articles.

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2. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60mV/dec;Choi;IEEE Electron Device Lett.,2007

3. Complementary tunneling transistor for low power application;Wang;Solid-state Electron.,2004

4. Performance comparisons of tunneling field-effect transistors made of InSb, carbon, and GaSb-InAs broken gap heterostructures;Luisier,2009

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4. Lower subthreshold swing and improved miller capacitance heterojunction tunneling transistor with overlapping gate;Materials Today: Proceedings;2021