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A clock synchronization method for EtherCAT master

  • Published:2016-10 Issue: Volume:46 Page:211-218
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Chen Xin,Li Di,Wan Jiafu,Zhou Nan

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference18 articles.

1. EtherCAT enabled advanced control architecture;Rostan,2010

2. Control and communication challenges in networked real-time systems;Baillieul;Proc. IEEE,2007

3. Improving fault tolerance in high-precision clock synchronization;Gaderer;IEEE Trans. Ind. Informat.,2010

4. On the seamless interconnection of IEEE1588-based devices using a PROFINET IO infrastructure;Paolo;IEEE Trans. Ind. Informat.,2010

5. Evaluation of EtherCAT distributed clock performance;Cena;IEEE Trans. Ind. Informat.,2012

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2. A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

3. General Evaluation of EtherCAT-Based Techniques in Various Industrial Systems: Review and Applications;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024

4. Emerging the real‐time performance for the single axis slave controller in the decentralised network;IET Collaborative Intelligent Manufacturing;2023-10-05

5. Innovation of EtherCAT adaptive synchronization control in embedded CNC;International Journal of Communication Systems;2023-02-27
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