A low-cost, fault-tolerant and high-performance router architecture for on-chip networks-Reference-Cited by-同舟云学术

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A low-cost, fault-tolerant and high-performance router architecture for on-chip networks

Published:2016-08 Issue: Volume:45 Page:151-163
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Valinataj Mojtaba^ORCID,Shahiri Mostafa

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference28 articles.

1. Power aware NoC reuse on the testing of core based systems;Cota,2003

2. Thousand core chips: a technology perspective;Borkar,2007

3. Crosstalk- and SEU-aware networks on chips;Frantz;IEEE Des. Test Comput.,2007

4. Reliable network-on-chip using a low cost unequal error protection code;Dutta,2007

5. Agent-based on-chip network using efficient selection method;Ebrahimi,2011

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A new architecture for online error detection and isolation in network on chip;Journal of High Speed Networks;2020-12-23

2. Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip;Electronics;2020-10-27

3. Protector: A Permanent Fault Resilient Router Architecture for Network on Chip;Mehran University Research Journal of Engineering and Technology;2020-10-01

4. Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things;Sensors;2020-09-18

5. NoCGuard: A Reliable Network-on-Chip Router Architecture;Electronics;2020-02-17

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