3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Author:

Xue Licheng,Shi Feng,Ji Weixing,Khan Haroon-Ur-Rashid

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. NxtSPR: A deadlock-free shortest path routing dedicated to relaying for Triplet-Based many-core Architecture;Parallel Computing;2024-09

2. A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory;Parallel Architectures, Algorithms and Programming;2020

3. An Efficient Distributed Minimal Routing Algorithm for Triplet-Based WK-recursive Network;2018 IEEE 20th International Conference on High Performance Computing and Communications; IEEE 16th International Conference on Smart City; IEEE 4th International Conference on Data Science and Systems (HPCC/SmartCity/DSS);2018-06

4. Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips;Microprocessors and Microsystems;2015-02

5. Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip;Procedia Computer Science;2015

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