Timing optimization via nest-loop pipelining considering code size

Author:

Zhuge Qingfeng,Xue Chun Jason,Qiu Meikang,Hu Jingtong,Sha Edwin H.-M.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference21 articles.

1. R. Bailey, D. Defoe, R. Halverson, R. Simpson, N. Passos, A study of software pipelining of multi-dimensional problems, in: Proceedings of the 13th International Conference on Parallel and Distributed Computing and Systems, August 2000, pp. 426–431.

2. N. Chabini, W. Wolf, An approach for integrating basic retiming and software pipelining, in: Proceedings of the 4th International Conference on Embedded Software, 2004, pp. 287–296.

3. Rotation scheduling: a loop pipelining algorithm;Chao;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1997

4. Static scheduling for synthesis of DSP algorithms on various models;Chao;Journal of VLSI Signal Processing,1995

5. Scheduling data-flow graphs via retiming and unfolding;Chao;IEEE Transactions on Parallel and Distributed Systems,1997

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1. Energy and memory-aware software pipelining streaming applications on NoC-based MPSoCs;Future Generation Computer Systems;2020-10

2. Synthesizing distributed pipelining systems with timing constraints via optimal functional unit assignment and communication selection;Journal of Computational Science;2018-05

3. Optimal functional-unit assignment and buffer placement for probabilistic pipelines;Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis;2016-10

4. Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines;2016 13th International Conference on Embedded Software and Systems (ICESS);2016-08

5. Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop Striping;2013 Euromicro Conference on Digital System Design;2013-09

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