Design and implementation of a queue compiler

Author:

Canedo Arquimedes,Abderazek Ben A.,Sowa Masahiro

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference33 articles.

1. Design and architecture for an embedded 32-bit QueueCore;Abderazek;Journal of Embedded Computing,2006

2. High-level modeling and FPGA prototyping of produced order parallel queue processor core;Abderazek;Journal of Supercomputing,2006

3. Clock rate versus ipc: the end of the road for conventional microarchitectures;Agarwal;ACM SIGARCH Computer Architecture News,2000

4. Compilers Principles;Aho,1986

5. Optimizing Compilers for Modern Architectures;Allen,2002

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multicore SoCs Design Methods;Advanced Multicore Systems-On-Chip;2017

2. Equivalent single-queue–single-server model for a Pentium processor;Applied Mathematical Modelling;2010-09

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