Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference51 articles.
1. J. Anderson, S. Brown, Technology mapping for large complex PLDs, in: Proceedings of Design Automation Conference, DAC’98, 1998, pp. 698–703.
2. J. Kim, S. Byun, H. Kim, Development of technology mapping algorithm for CPLD under time constraint, in: 6th International Conference on VLSI and CAD, ICVC ’99, 1999, pp. 411–414.
3. A. Kaviani, S. Brown, Technology mapping issues for an FPGA with lookup tables and PLA-like blocks, in: Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays, 2000, pp. 60–66.
4. Digital Systems Design with Programmable Logic;Bolton,1990
5. Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition;Kania,1999
Cited by
23 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献