Author:
Suaganthy M.,Karthikeyan A.,Kuppusamy P.G.
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference12 articles.
1. Near shannon limit error-correcting coding and decoding: turbo-codes. 1;Berrou,1993
2. From Parallelism levels to a multi-asip architecture for turbo decoding;Muller;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2009
3. A reconfigurable asip for convolutional and turbo decoding in an SDR environment;Vogt;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2008
4. Improving network-on-chip-based turbo decoder architectures;Martina;J. Signal Process. Syst.,2013
5. Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures;Martina;IEEE Trans. Circuits Syst. I, Reg. Papers,2010
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献