A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS

Author:

Nguyen Xuan-ThuanORCID,Hoang Trong-ThucORCID,Nguyen Hong-Thu,Inoue Katsumi,Pham Cong-Kha

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

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5. High-speed and low-power CMOS priority encoders;Wang;IEEE J. Solid-State Circuits,2000

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1. 64-bit Multi-match Priority Encoder (MPE64) for High Performance VLSI Architectures;2022 2nd International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC);2022-01-21

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