A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Author:

Jackson Chris,Hollis Simon J.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference35 articles.

1. The future of multiprocessor systems-on-chips;Wolf,2004

2. Route packets, not wires: on-chip inteconnection networks;Dally,2001

3. On-chip communication architecture exploration: a quantitative evaluation of point-to-point, bus, and network-on-chip approaches;Lee;ACM Trans. Des. Autom. Electron. Syst.,2007

4. A survey of research and practices of network-on-chip;Bjerregaard;ACM Comput. Surv.,2006

5. Key research problems in NoC design: a holistic perspective;Ogras,2005

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1. Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications;Micromachines;2023-10-07

2. Fault-Tolerant Routing in Networks-on-Chip Using Self-Organizing Routing Algorithms;IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society;2021-10-13

3. A Multihoming ACO-MDV Routing for Maximum Power Efficiency in an IoT Environment;Wireless Personal Communications;2019-05-15

4. A scalable and adaptable hardware NoC-based self organizing map;Microprocessors and Microsystems;2018-03

5. NoC routing protocols – objective-based classification;Journal of Systems Architecture;2016-05

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