Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge
Author:
Publisher
Elsevier BV
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference20 articles.
1. Deep neural network hardware implementation based on stacked sparse autoencoder;Coutinho;IEEE Access,2019
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4. FPGA acceleration on a multi-layer perceptron neural network for digit recognition;Westby;J. Supercomput.,2021
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