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Ascon hardware implementations and side-channel evaluation

Published:2017-07 Issue: Volume:52 Page:470-479
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Gross Hannes,Wenger Erich,Dobraunig Christoph,Ehrenhöfer Christoph

Funder

Austrian Science Fund

European Commission

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference20 articles.

1. NORX;Aumasson,2014

2. CAESAR: competition for authenticated encryption: security, applicability, and robustness;Bernstein,2014

3. Keccak specifications;Bertoni,2011

4. Efficient and first-order DPA resistant implementations of keccak;Bilgin,2014

5. A more efficient AES threshold implementation;Bilgin,2014

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM;Electronics;2024-09-04

2. Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher;International Journal of Information Security;2024-08-29

3. Efficiency and Security Evaluation of Lightweight Cryptographic Algorithms for Resource-Constrained IoT Devices;Sensors;2024-06-20

4. PACAC: PYNQ Accelerated Cardiac Arrhythmia Classifier with secure transmission- A Deep Learning based Approach;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

5. A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

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