Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA-Reference-Cited by-同舟云学术

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Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA

Published:2017-06 Issue: Volume:51 Page:220-226
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Miškovský Vojtěch,Kubátová Hana,Novotný Martin

Funder

Czech Grant Agency

CTU

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference23 articles.

1. Evaluation of a soft error tolerance technique based on time and/or space redundancy;Anghel,2000

2. An automated BIST architecture for testing and diagnosing FPGA interconnect faults;Smith;J. Electron. Test.,2006

3. Low overhead fault-tolerant FPGA systems;Lach;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,1998

4. Fault tolerant methods for reliability in FPGAs;Stott,2008

5. Securing the AES finalists against power analysis attacks;Messerges,2000

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A dual mode self-test for a stand alone AES core;PLOS ONE;2021-12-23

2. Design of a BIST implemented AES crypto-processor ASIC;PLOS ONE;2021-11-16

3. QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks;ACM Transactions on Design Automation of Electronic Systems;2021-06-05

4. CMOS Illumination Discloses Processed Data;2019 22nd Euromicro Conference on Digital System Design (DSD);2019-08

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