An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults

Author:

Smith Jack,Xia Tian,Stroud Charles

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference15 articles.

1. M. Abramovici and C. Stroud, “BIST-Based Delay-Fault Testing in FPGAs,” Proc. Int’l On-Line Testing Workshop, 2002, pp. 131–134.

2. M. Abramovici and C. Stroud, “BIST-Based Delay Fault Testing in Field Programmable Gate Arrays,” J. Electronic Testing: Theory & Applications, vol. 19, no. 5, pp. 549–558, 2003.

3. E. Chmelar, “FPGA Interconnect Delay Fault Testing,” Proc. Int’l Test Conf., 2003, pp. 1239–1247.

4. http://www.xilinx.com

5. J. Liu and S. Simmons, “BIST-Diagnosis of Interconnect Fault Locations in FPGAs,” Proc. Canadian Conf. on Electrical and Computer Engineering, 2003, pp. 207–210.

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