Finding the best compromise in compiling compound loops to Verilog-Reference-Cited by-同舟云学术

Finding the best compromise in compiling compound loops to Verilog

Published:2010-09 Issue:9 Volume:56 Page:474-486
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Ben-Asher Yosi,Rotem Nadav,Shochat Eddie

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference29 articles.

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4. S. Bhattacharya, S. Dey, F. Brglez, Performance analysis and optimization of schedules for conditional and loop-intensive specifications, in: DAC ’94, 1994.

5. Path-based scheduling for synthesis;Camposano;IEEE Trans. Comput. Aided Des.,1991

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