Author:
Neishaburi M.H.,Zilic Zeljko
Subject
Hardware and Architecture,Software
Reference50 articles.
1. W.J. Dally, B. Towles, Route packets not wires: on-chip interconnection networks, in: Proceedings of Design Automation Conference (DAC), 2001, pp. 684–689.
2. H. Wang, et al., A detailed architectural-level power model for router buffers, crossbars and arbiters, Technical report, Princeton University, 2004.
3. A. Kumar, P. Kundu, A.P. Singh, L. Peh, N. Jha, 4.6 T bits/s 3.6 GHz Single-cycle NoC router with a Novel Switch Allocator in 65nm CMOS, in: Proceedings of International Conference on Computer Design (ICCD), 2007, pp. 63–70.
4. Available from: .
5. Available from: .
Cited by
8 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献