Verifying parallel dataflow transformations with model checking and its application to FPGAs

Author:

Stewart Robert,Berthomieu Bernard,Garcia Paulo,Ibrahim Idris,Michaelson Greg,Wallace Andrew

Funder

Engineering and Physical Research Council

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference43 articles.

1. Power efficient dataflow design for a heterogeneous smart camera architecture;Bhowmik,2017

2. RIPL: A Parallel Image processing language for FPGAs;Stewart;TRETS,2018

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