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Model checking of MARTE/CCSL time behaviors using timed I/O automata

  • Published:2018-08 Issue: Volume:88 Page:120-125
  • ISSN:1383-7621
  • Container-title:Journal of Systems Architecture
  • language:en
  • Short-container-title:Journal of Systems Architecture

Author:

Chen BoORCID,Li Xi,Zhou Xuehai

Funder

Suzhou

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference16 articles.

1. A predictable framework for safety-critical embedded systems;Andalam;IEEE Trans. Comput.,2014

2. Clock constraints in uml/marte ccsl, Ph.D. thesis;André,2008

3. Verifying marte/ccsl mode behaviors using uppaal;Suryadevara,2013

4. N.A. Lynch, M.R. Tuttle, An introduction to input/output automata (1988).

5. Timesquare: treat your models with logical time;DeAntoni;Objects Models Compon. Patterns,2012

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1. Formal verification of reconfigurable systems;Soft Computing;2023-05-06

2. From UML/MARTE Specifications to ESL HW/SW Co-Design: Early Functional Verification and Timing Validation;Companion of the 2023 ACM/SPEC International Conference on Performance Engineering;2023-04-15

3. A Model-Driven Approach for Early Verification and Validation of Embedded Systems;2021 ACM/IEEE International Conference on Model Driven Engineering Languages and Systems Companion (MODELS-C);2021-10

4. A clock-based dynamic logic for the verification of CCSL specifications in synchronous systems;Science of Computer Programming;2021-03

5. Multiclock Constraint System Modelling and Verification for Ensuring Cooperative Autonomous Driving Safety;Journal of Advanced Transportation;2020-12-05
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