A clock-based dynamic logic for the verification of CCSL specifications in synchronous systems-Reference-Cited by-同舟云学术

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A clock-based dynamic logic for the verification of CCSL specifications in synchronous systems

Published:2021-03 Issue: Volume:203 Page:102591
ISSN:0167-6423
Container-title:Science of Computer Programming
language:en
Short-container-title:Science of Computer Programming

Author:

Zhang Yuanrui,Wu Hengyang,Chen Yixiang,Mallet Frédéric

Funder

EUR DS4H

ANR

Publisher

Elsevier BV

Subject

Software

Reference46 articles.

1. Clock constraint specification language: specifying clock constraints with UML/MARTE;Mallet;Innov. Syst. Softw. Eng.,2008

2. Syntax and semantics of the clock constraint specification language (CCSL);André,2009

3. UML profile for MARTE: modeling and analysis of real-time embedded systems;OMG,2011

4. pCSSL: a stochastic extension to MARTE/CCSL for modeling uncertainty in cyber physical systems;Du;Sci. Comput. Program.,2018

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Specification and Verification of Multi-Clock Systems Using a Temporal Logic with Clock Constraints;Formal Aspects of Computing;2024-06-26

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