Silicon-aware distributed switch architecture for on-chip networks

Author:

Roca Antoni,Hernández Carles,Flich José,Silla Federico,Duato José

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference42 articles.

1. Designing Network On-Chip Architectures in the Nanoscale Era, Computational Science Series;Flich,2010

2. Networks on Chips: Technology and Tools, in Systems on Silicon;de Micheli,2006

3. R. Ho, K.W. Mai, S. Member, M.A. Horowitz, The future of wires, in: Proceedings of the IEEE, 2001, pp. 490–504.

4. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints;Chen;IEEE Trans. VLSI Syst.,2006

5. An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures;Flores;J. Supercomput.,2008

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1. A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study;IEEE Access;2023

2. Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers;IEEE Transactions on Computers;2017-04-01

3. ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-12

4. On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck;Proceedings of the 9th International Symposium on Networks-on-Chip;2015-09-28

5. The fast evolving landscape of on-chip communication;Design Automation for Embedded Systems;2014-04-30

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