A superscalar architecture to exploit instruction level parallelism-Reference-Cited by-同舟云学术

A superscalar architecture to exploit instruction level parallelism

Published:1997-03 Issue:7 Volume:20 Page:391-400
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Steven Gordon,Christianson Bruce,Collins Roger,Potter Richard,Steven Fleur

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference29 articles.

1. Superscalar Microprocessor Design;Johnson,1991

2. Very long instruction set architectures and the ELI-512;Fisher,1983

3. The Hatfield Superscalar Architecture: Version 2;Steven;University of Hertfordshire Technical Report,1994

4. Limits of instruction level parallelism;Wall,1991

5. Using a resource limited instruction scheduler to evaluate the iHARP Processor;Steven,1995

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