Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters
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Publisher
IntechOpen
Link
http://www.intechopen.com/download/pdf/70543
Reference7 articles.
1. BenSaleh MS, Qasim SM, AlJuffri AA, Obeid AM. Scalable design of microprogrammed digital FIR filter for sensor processing subsystem. IEICE Electronics Express. 2014;11:1-7. DOI: 10.1587/elex.11.20140474
2. Qasim SM, BenSaleh MS. Hardware implementation of microprogrammed controller based digital FIR filter. IAENG Transactions on Engineering Technologies. 2014;247:29-40. DOI: 10.1007/978-94-007-6818-5_3
3. Qasim SM, BenSaleh MS, Bahaidarah M, AlObaisi H, AlSharif T, Alzahrani M, et al. Design and FPGA implementation of sequential digital FIR filter using microprogrammed controller. In: Proceedings of IV IEEE International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT’12); 3-5 October 2012. St. Petersburg, Russia: IEEE; 2012. pp. 1002-1005
4. Waters R, Swartzlander E. A reduced complexity Wallace multiplier reduction. IEEE Transactions on Computers. 2010;59:1134-1137. DOI: 10.1109/TC.2010.103
5. Xing S, Yu WWH. FPGA adders: Performance evaluation and optimal design. IEEE Design and Test of Computers. 1998;15:24-29. DOI: 10.1109/54.655179
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