Low-Latency Asynchronous Logic Design for Inference at the Edge

Author:

Wheeldon Adrian,Yakovlev Alex,Shafik Rishad,Morris Jordan

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

2. Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

3. A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System;TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON);2023-10-31

4. Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

5. MILEAGE: An Automated Optimal Clause Search Paradigm for Tsetlin Machines;2022 International Symposium on the Tsetlin Machine (ISTM);2022-06

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