112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8766307/8777931/08778136.pdf?arnumber=8778136
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09
2. A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET;IEEE Journal of Solid-State Circuits;2023-08
3. A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers;Electronics;2022-10-27
4. A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers;Electronics;2022-07-13
5. ADC-Based SerDes Receiver for 112 Gb/s PAM4 Wireline Communication;Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication;2022
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