0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur-Reference-Cited by-同舟云学术

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0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Published:2019-06 Issue: Volume: Page:
ISSN:
Container-title:2019 Symposium on VLSI Circuits
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Author:

Zhang Haosheng,Narayanan Aravind Tharayil,Herdian Hans,Liu Bangan,Wang Yun,Shirane Atsushi,Okada Kenichi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8766307/8777931/08778059.pdf?arnumber=8778059

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 28.8-to-43.2 GHz 79.8 fs_rms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration;IEEE Transactions on Microwave Theory and Techniques;2024-05

2. 19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. A 2.4-GHz complementary voltage-controlled oscillator (VCO) for bluetooth-low-energy (BLE) internet-of-things (IoT) application;AIP Conference Proceedings;2024

4. A 14.2 mW 29-39.3-GHz Two-Stage PLL with a Current-Reuse Coupled Mixer Phase Detector;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11

5. A Cryo-CMOS PLL for Quantum Computing Applications;IEEE Journal of Solid-State Circuits;2023-05

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