A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm-Reference-Cited by-同舟云学术

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A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

Published:2019-06 Issue: Volume: Page:
ISSN:
Container-title:2019 Symposium on VLSI Circuits
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Author:

Pal Subhankar,Park Dong-hyeon,Feng Siying,Gao Paul,Tan Jielun,Rovinski Austin,Xie Shaolin,Zhao Chun,Amarnath Aporva,Wesley Timothy,Beaumont Jonathan,Chen Kuan-Yu,Chakrabarti Chaitali,Taylor Michael,Mudge Trevor,Blaauw David,Kim Hun-Seok,Dreslinski Ronald

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8766307/8777931/08778147.pdf?arnumber=8778147

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Sparse-Aware Summation Optimization Strategy for DNN Accelerator;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET;IEEE Journal of Solid-State Circuits;2024

3. An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-04

4. OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators;ACM Transactions on Embedded Computing Systems;2022-10-18

5. A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-10

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